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 NCP5208 DDR-I/II Termination Regulator
The NCP5208 is a linear regulator specifically designed for the active termination of DDR-I/II SDRAM. The device can be operated from a single supply voltage as low as 1.7 V. For DDR-I applications, the device is capable of sourcing and sinking current up to 1.5 A with the output voltage regulated to within "3% or better. A separate voltage feedback pin ensures superior load regulation against load and line changes. Protective features include soft-start, source/sink current limits and thermal shutdown. Open-drain VTT OK output (POK) is added for system monitoring. The shutdown pin can tri-state the regulator output for Suspend To RAM (STR) state. This device is available in a SO-8 package.
Features
http://onsemi.com MARKING DIAGRAM
8 8 1 SO-8 D SUFFIX CASE 751 1 A L Y W = Assembly Location = Wafer Lot = Year = Work Week N5208 ALYW
* * * * * * * * * * *
Supports Both DDR-I and DDR-II SDRAM Requirements Single Supply Voltage Operation as Low as 1.7 V Integrated Power MOSFETs Few External Components Needed Source and Sink Current Up to 1.5 A Load Regulation Within "3% Both Source and Sink Current Limits Open-Drain VTT OK (POK) Pin Shutdown Pin Thermal Shutdown Housed in SO-8 Package
PIN CONNECTIONS
POK 1 GND 2 VFB 3 SD 4 (Top View) 8 7 6 5 VTT PVIN AVIN VDDQ
Typical Applications
* DDR Termination Voltage * Active Bus Termination (SSTL-2, SSTL-3)
VDDQ 2.5 V VDDQ AVIN SD
ORDERING INFORMATION
Device NCP5208DR2 Package SO-8 Shipping 2500 Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
NCP5208
POK AVIN PVIN CIN VTT VFB VTT 1.25 V, 1.5 A COUT
2.5 V
GND
Figure 1. Typical Application Circuit
(c) Semiconductor Components Industries, LLC, 2004
1
February, 2004 - Rev. 3
Publication Order Number: NCP5208/D
NCP5208
VDDQ VDDQ AVIN R - M0 EN SD + - EN R/50 AVIN COUT M1 R EN VFB VTT + VTT POK AVIN AVIN PVIN PVIN
GND
Figure 2. Simplified Functional Block Diagram PIN FUNCTION DESCRIPTION
Pin 1 2 3 4 5 6 7 8 Symbol POK GND VFB SD VDDQ AVIN PVIN VTT Open-drain VTT Power OK output Ground Remote sensing Feedback pin for regulating VTT Active low shutdown pin to tri-state VTT output, this pin is pulled high internally Reference input for VTT regulator Analog supply input, this powers all the internal control circuitry Power supply input, this provides the rail voltage for the VTT output Termination Regulator output Description
MAXIMUM RATINGS
Rating AVIN, PVIN, VDDQ, VFB, VTT to GND Input/Output Pins Open Drain Output Pins Thermal Characteristics SO-8 Package Thermal Resistance, Junction-to-Air Operating Junction Temperature Range Operating Ambient Temperature Range Storage Temperature Range 1. This device series contains ESD protection and exceeds the following tests: Human Body Model (HBM) v2.0 kV per JEDEC standard: JESD22-A114. Machine Model (MM) v200 V per JEDEC standard: JESD22-A115. 2. Latch-up Current Maximum Rating: "150 mA per JEDEC standard: JESD78. SD POK Symbol - VIO VPOK RqJA_T Value -0.3, 6.0 -0.3, 6.0 -0.3, 6.0 151 Unit V V V C/W
TJ TA Tstg
-10 to +150 0 to +70 -55 to +150
C C C
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NCP5208
ELECTRICAL CHARACTERISTICS (AVIN = 2.5 V, PVIN = 2.5 V, VDDQ = 2.5 V, COUT = 220 mF, for typical values TA = 25C, for min/max values TA = 0 to 70C, unless otherwise noted.)
Characteristic Analog Supply Input Power Supply Input Termination Voltage Output Symbol AVIN PVIN VTT Conditions - - AVIN = 2.5 V, VDDQ = PVIN = 1.8 V IVTT = -0.6 A to +0.6 A AVIN = PVIN = VDDQ = 2.5 V IVTT = -1.5 A to 1.5 A Load Regulation DVTT VDDQ = 1.8 V, IVTT = 0 to +0.6 A VDDQ = 1.8 V, IVTT = 0 to -0.6 A VDDQ = 2.5 V, IVTT = 0 to +1.5 A VDDQ = 2.5 V, IVTT = 0 to -1.5 A Analog Current Consumption VDDQ Input Impedance VFB Feedback Pin Input Current SHUTDOWN CONTROL Shutdown Pin Enable Threshold Shutdown Pin Hysteresis Shutdown Pin Input Current VSD VSDhys ISD - - VDDQ = 2.5 V, VSD = 0 V VDDQ = 2.5 V, VSD = 2.5 V VDDQ = 2.5 V, VSD = 5.5 V VDDQ = 2.5 V, VSD = 0 V 1.14 0.40 -15 - - - 1.24 0.55 - - - - VDDQ x (1/2-0.02) VDDQ x (1/2+ 0.02) - - 1.34 0.68 - 10 12 15 V V mA IAVIN ZVDDQ IVFB No Load - Note 3 Min 1.7 1.7 0.870 1.215 - -18 - -20 - - - Typ - - 0.900 1.250 - - - - - 50 - Max 5.5 AVIN 0.930 1.285 15 - 20 - 10 - 20 Unit V V V V mV mV mA kW nA
Shutdown Analog Supply Current VTT POWER OK INDICATOR VTT Power OK Window Low Threshold VTT Power OK Window High Threshold POK Pull-LOW Resistance POK Leakage Current OVER CURRENT PROTECTION Source Current Limit Sink Current Limit OVER TEMPERATURE PROTECTION Thermal Shutdown Temperature Thermal Shutdown Hysteresis
Ishut
mA
POKLth POKHth RPOKL IPOKleak
Note 4 Note 4 IPOK = 5.0 mA VDDQ = 2.5 V, VPOK = 6.0 V
- - 7.0 -
- - 20 0.1
V V W mA
ILIMsrc ILIMsnk
- -
1.65 -2.9
2.1 -2.0
2.9 -1.65
A A C C
TSD TSDhys
Note 3 Note 3
120 -
135 30
150 -
3. Values are not tested in production, guaranteed by design only. 4. Production test performed for AVIN = PVIN = VDDQ = 2.5 V only, 1.8 V performance guaranteed by design.
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NCP5208
TYPICAL OPERATING CHARACTERISTICS
0.950 AVIN = 2.5 V PVIN = VDDQ = 1.8 V TA = 25C 1.300 AVIN = 2.5 V PVIN = VDDQ = 2.5 V TA = 25C
VTT, Output Voltage (V)
0.925
VTT, Output Voltage (V) 0.8
1.275
0.900
1.250
0.875
1.225
0.850 -0.8
0.4 -0.6 -0.4 -0.2 0 0.2 0.6 IVTT, OUTPUT LOAD CURRENT (A)
1.200 -1.8
-1.4 -1.0 -0.6 -0.2 0.2 0.6 1.0 1.4 IVTT, OUTPUT LOAD CURRENT (A)
1.8
Figure 3. VTT Output Voltage vs. Load Current (VDDQ = 1.8 V)
VTT, Source Current Load Regulation (mV) 0 -2 -4 -6 -8 -10 -12 -14 -16 -18 -20 0 PVIN = VDDQ, = AVIN = 2.5 V 10 60 20 30 40 50 TA, AMBIENT TEMPERATURE (C) 70 VDDQ = 2.5 V, IVTT = 1.5 A VDDQ = 1.8 V, IVTT = 0.6 A
Figure 4. VTT Output Voltage vs. Load Current (VDDQ = 2.5 V)
20 18 16 14 12 10 8 6 4 2 0 0 10 60 20 30 40 50 TA, AMBIENT TEMPERATURE (C) 70 VDDQ = 1.8 V, IVTT = 0.6 A VDDQ = 2.5 V, IVTT = 1.5 A PVIN = VDDQ, = AVIN = 2.5 V
Figure 5. Source Current Load Regulation vs. Ambient Temperature
VTT, Sink Current Load Regulation (mV)
Figure 6. Sink Current Load Regulation vs. Ambient Temperature
2.5 ILIM, Over Current Protection Limit (A) Source Current 2.0 Sink Current 1.5 IAVIN, Analog Input Current (mA)
10 PVIN = AVIN = VDDQ = 2.5 V IVTT = 0 A 8
6
1.0
4
0.5 PVIN = AVIN = VDDQ = 2.5 V 0 0 10 20 30 40 50 60 TA, AMBIENT TEMPERATURE (C) 70
2 0 0 10 20 30 40 50 60 TA, AMBIENT TEMPERATURE (C) 70
Figure 7. Over Current Protection Limit vs. Ambient Temperature
Figure 8. Analog Input Current vs. Ambient Temperature
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NCP5208
TYPICAL OPERATING CHARACTERISTICS
55 ZVDDQ, VDDQ Input Impedance (W)
52
49
46 PVIN = AVIN = VDDQ = 2.5 V IVTT = 0 A
43 40 0
10
20 30 40 50 60 TA, AMBIENT TEMPERATURE (C)
70
Figure 9. VDDQ Input Impedance vs. Ambient Temperature
TYPICAL OPERATING WAVEFORMS
0.4 ms ON, 1.6 ms OFF 0.4 ms ON, 1.6 ms OFF
(PVIN = AVIN = VDDQ = 1.8 V) Upper Trace: VTT Output Waveform, 50 mV/Division, AC Coupled Lower Trace: Loading Current, IVTT, 500 mA/Division
(PVIN = AVIN = VDDQ = 1.8 V) Upper Trace: VTT Output Waveform, 50 mV/Division, AC Coupled Lower Trace: Loading Current, IVTT, 500 mA/Division
Figure 10. VTT Current Source Transient
Figure 11. VTT Current Sink Transient
0.4 ms ON, 1.6 ms OFF
0.4 ms ON, 1.6 ms OFF
(PVIN = AVIN = VDDQ = 2.5 V) Upper Trace: VTT Output Waveform, 50 mV/Division, AC Coupled Lower Trace: Loading Current, IVTT, 1 A/Division
(PVIN = AVIN = VDDQ = 2.5 V) Upper Trace: VTT Output Waveform, 50 mV/Division, AC Coupled Lower Trace: Loading Current, IVTT, 1 A/Division
Figure 12. VTT Current Source Transient http://onsemi.com
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Figure 13. VTT Current Sink Transient
NCP5208
TYPICAL OPERATING WAVEFORMS
(PVIN = AVIN = VDDQ = 2.5 V, IVTT = 0 A) Upper Trace: VTT Output Waveform, 500 mV/Division Middle Trace: VTT Power OK Output, 2 V/Division Lower Trace: Shut-down Signal, 1 V/Division Time Scale: 500 ms/Division
(PVIN = AVIN = VDDQ = 1.8 V, IVTT = 0 A) Upper Trace: VTT Output Waveform, 500 mV/Division Middle Trace: VTT Power OK Output, 2 V/Division Lower Trace: Shut-down Signal, 1 V/Division Time Scale: 500 ms/Division
Figure 14. VTT Start-up Waveform (VDDQ = 2.5 V)
Figure 15. VTT Start-up Waveform (VDDQ = 1.8 V)
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NCP5208
DETAILED OPERATING DESCRIPTIONS
General Termination Voltage Output Regulation
The NCP5208 is a linear regulator with both sink and source current capabilities used for active termination of fast switching logic, DDR-I/II SDRAM terminations and active buses termination of SSTL-2/3 logic. This device can be operated from a single supply voltage as low as 1.7 V. For DDR-I applications, the device is capable of sourcing and sinking current up to 1.5 A with output voltage regulated to within 3%. The separate voltage remote feedback pin ensures superior load and line regulation with fast tracking capability. Protective features include Soft-Start, Source/Sink Current Limits and internal Thermal Shutdown. Additionally, an open-drain VTT OK output signal (POK) is provided for system monitoring. The shutdown pin (SD) can be used to tri-state the regulator output for Suspend To RAM (STR) state. This device is available in a low profile, space saving SO-8 package.
Supply Voltage Inputs
The NCP5208 includes a simple linear series regulator with a pair of control error amplifiers, which takes care of the current source and sink operations separately. The error amplifiers control a pair of MOSFETs to maintain the output voltage equal to the internal reference voltage for both current sink and source conditions. In order to avoid the MOSFETs turning on at the same time, a dead-band is implemented internally for safe operation.
Regulator Shutdown Function
The operation of the NCP5208 can be suspended by pulling the Shutdown (SD) pin to ground. When the device is stopped, the regulator output will be tri-stated for Suspend To RAM (STR) state in PC applications. The shutdown pin is internally pulled high by a small current source, if this feature is not used, this pin can be left open.
VTT Power OK for System Monitoring
For added flexibility, separate input pins are provided for each required supply input. AVIN is the device operating voltage, VDDQ is used to generate the internal reference for VTT output voltage control and PVIN is the power rail for the linear regulator. The device will regulate the output voltage, VTT, with respect to the internal voltage reference generated from VDDQ input and track the VDDQ changes closely. The separate PVIN pin allows the designer to isolate the high current PVIN line changes from coupling into the noise sensitive AVIN and VDDQ inputs. Since the AVIN supplies the control to the output power MOSFETs, PVIN should always be lower than or equal to AVIN.
Generation of Internal Reference Voltage
NCP5208 provides an additional VTT power OK signal for system monitoring. The VTT Power OK (POK) pin goes low when the VTT voltage is in regulation and has settled within the allowed window. For memory termination applications, the system can check this pin to ensure the termination voltage quality before accessing the memory. The POK output is connected to a open-drain switching FET and the designer is free to pull this pin to any logic voltage level externally. When the VTT output is in regulation, the internal FET is turned on and pulls the power OK pin to ground.
Over-current Protection for Sink and Source Operation
The prime function of a termination regulator is to provide a termination voltage, VTT at its output, which can track the mid-point of the logic voltage level closely, i.e. 1/2(VDDQ). The VTT voltage is used to terminate the bus resistors. The NCP5208 generates a precise reference voltage internally with a built in dead-band to avoid upper and lower MOSFET shoot through.
Remote Voltage Feedback Sensing
In order to provide protection for the internal power MOSFETs, bi-directional current limit protection circuits are implemented. Current limit levels are internally set at 2.1 A typical for current source and 2.0 A typical for current sink at 2.5 V operation.
Thermal Shutdown with Hysteresis
To guarantee safe operation, NCP5208 provides on-chip thermal shutdown protection. When the chip junction temperature exceeds 135_C typical, the part will shutdown. When the junction temperature falls back to 105_C typical, the device resumes normal operation.
The NCP5208 has a separate feedback pin to monitor the output voltage at the remote point. With this capability, the output voltage can be controlled precisely at the output capacitor so that any noise and fluctuations along the power path can be eliminated.
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NCP5208
APPLICATIONS INFORMATION
Typical Application Circuit Thermal Dissipation
The NCP5208 is a highly integrated termination regulator. For most applications, an input and output capacitor and a pull-up resistor for the power OK output, are the only external components needed. For typical application circuit, refer to Figure 1.
AVIN and VDDQ Supply
AVIN provides power for the device to operate. This voltage must be kept clean and free from transients. A small capacitor, 1.0 mF is recommended at this input to provide the required supply filtering and ripple rejection. VDDQ is primarily used to generate the internal voltage reference, so any noise or transient at this pin will be directly reflected at the VTT output. In order to avoid undesired interference injected into this pin, appropriate de-coupling and careful design of PCB layout is required.
Input Capacitor Selection
The NCP5208 is a linear regulator, any current flow from/to VTT will result in internal power dissipation and generating heat. In order to prevent un-wanted shutdown of the device during operation, care should be taken to de-rate the power capability according to the maximum expected ambient temperature and power dissipation. The maximum allowable internal temperature rise, TR-MAX can be calculated from the equation in below:
TR-MAX + TJ-MAX * TA-MAX
Where TJ-MAX is the maximum allowable junction temperature and TA-MAX is the maximum expected ambient temperature. The maximum allowable power dissipation for a specific condition is given by:
T PD-MAX + R-MAX RqJA_T
The NCP5208 does not require an input capacitor for stability, however it is still recommended for better overall performance during large load transients that can cause sudden drop of the power rail voltage. The input capacitor must be located as close as possible to the PVIN pin to avoid a transient voltage dip affecting the quality of AVIN and VDDQ. For typical DDR-I applications, a low ESR electrolytic capacitor of 100 mF or larger is recommended. By adding a small ceramic capacitor of 0.1 mF in parallel, the best high frequency transient filtering will result. If the device is located near the main supply bulk capacitors, the input capacitance can be reduced accordingly.
Output Capacitor Selection
Where PD-MAX is the maximum allowable power dissipation and RJA_T is Junction-to-Air thermal resistance for specific package. The thermal handling capability depends on several variables. Increasing the thickness and area of the copper and adding vias and airflow can improve the thermal performance.
The NCP5208 is internally compensated and stable for any output capacitor with capacitance greater than 220 mF and with ESR ranging from 2 mW to 400 mW. The choice for this output capacitor is determined solely by the application and the requirements for load transient characteristic of VTT output. As a general recommendation, the capacitance should be larger than 220 mF with low ESR for SSTL and DDR memory applications.
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NCP5208
PACKAGE DIMENSIONS
SO-8 D SUFFIX CASE 751-07 ISSUE AA
-X- A
8 5 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751-01 THRU 751-06 ARE OBSOLETE. NEW STANDARD IS 751-07. MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244
B
1 4
S
0.25 (0.010)
M
Y
M
-Y- G C -Z- H D 0.25 (0.010)
M SEATING PLANE
K
N
X 45 _
0.10 (0.004)
M
J
ZY
S
X
S
DIM A B C D G H J K M N S
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NCP5208
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: N. American Technical Support: 800-282-9855 Toll Free Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Phone: 81-3-5773-3850 Email: orderlit@onsemi.com ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative.
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NCP5208/D


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